1. Field of the Invention
The present invention relates to a non-volatile memory and fabricating method thereof, and more particularly, to a flash memory having a non-symmetrical spacer structure and method of fabricating the same.
2. Description of Related Art
A typical flash memory has a floating gate and a control gate fabricated using doped polysilicon. To program data into the memory, suitable programming voltages are applied to the source, the drain and the control gate of a flash memory cell, so electrons can flow from the source to the drain through a channel. In the foregoing process, some of the electrons may penetrate through a tunneling oxide layer underneath the polysilicon floating gate and distribute evenly across the entire polysilicon gate. This phenomenon of electrons penetrating through the tunneling oxide layer into the polysilicon gate is called tunneling effect. In general, tunneling effect can be classified according to the conditions into the so-called channel hot-electron injection and the so-called Fowler-Nordheim (F-N) tunneling. Data is normally programmed into a flash memory through channel-hot electron injection and erased from the flash memory through source-side or channel area F-N tunneling.
FIGS. 1A and 1B are schematic cross-sectional views showing the process of fabricating a conventional flash memory.
As shown in FIG. 1A, a substrate is provided. Then, a tunneling oxide layer 102, a floating gate layer 104, an inter-gate dielectric layer 106 and a control gate layer 108 are sequentially formed over the substrate. Afterwards, an ion implant process 112 is performed to form a doped region 114 in the substrate 100 on the sides of the floating gate 104, respectively.
As shown in FIG. 1B, an annealing process 116 is performed to activate the doped region (refer to 114 in FIG. 1A) so that a source 118a and a drain 118b are formed in the substrate 100. The ion implant process 112 in FIG. 1A may damage a portion of the exposed edges of the tunneling oxide layer 102 and lead to degradation of the tunneling oxide layer 102 that affects the reliability of the device. Therefore, an additional thermal oxidation process is performed when the source 118a and the drain 118b are formed so that the tunneling oxide layer 102 is re-oxidized to increase the thickness of the exposed edges 102a. As a result, the tunneling oxide layer is re-strengthened and electrical stress in this region is reduced.
However, as shown in FIG. 1B, thickness tedge at the edge of the tunneling oxide layer 102 or the inter-gate dielectric layer 106 is thicker than thickness tcenter at the center. This difference in thickness is a big disadvantage to control of the gate-coupling ratio (GCR) between the floating gate and the control gate and may affect the operating voltage and speed of the device. Furthermore, the area between the tunneling oxide layer 102 and the channel (that is, the area between the source 118a and the drain 118b) is related to the erase operation of the flash memory. The increased edge thickness of the tunneling oxide layer 102 is also a big disadvantage to the erasing operation provided by the device.